产品详情

■ High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1) ■ 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ISP circuitry compliant with IEEE Std. 1532 ■ Built–in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 ■ Enhanced ISP features: – Enhanced ISP algorithm for faster programming – ISP_Done bit to ensure complete programming – Pull-up resistor on I/O pins during in–system programming ■ High–density PLDs ranging from 600 to 10,000 usable gates ■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to 227.3 MHz ■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V, while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic levels ■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier (PLCC), and FineLine BGATM packages ■ Hot–socketing support ■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance ■ Industrial temperature range

产品：  MAX 3000A

大电池数量：    128

逻辑数组块数量——LAB：    8

工作频率： 192.3 MHz

延迟时间：  5 ns

输入/输出端数量：   80

工作电源电压： 3.3 V

工作温度： + 70 C

安装风格：  SMD/SMT

封装 / 箱体：   TQFP-100

商标：  Altera Corporation

存储类型：  EEPROM

工作温度： 0 C

栅极数量：  2500

每个宏指令的积项数：    32

封装：  Tray

系列：  MAX 3000A

工厂包装数量： 90

电源电压-： 3.6 V

电源电压-： 3 V

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